XC3S100E Datasheet, PDF (49/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
BUFG
FPGA
CLK90
CLKIN
CLK180
CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
BUFGMUX
Clock
Net Delay
BUFGMUX
CLK0
(a) On-Chip with CLK0 Feedback
FPGA
IBUFG
IBUFG
CLK90
CLK180
CLKIN CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
OBUF
OBUF
Clock
Net Delay
BUFG
FPGA
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
BUFGMUX
Clock
Net Delay
CLKFB
CLK2X
BUFGMUX
CLK2X
(b) On-Chip with CLK2X Feedback
FPGA
IBUFG
IBUFG
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
OBUF
CLKFB
CLK2X
OBUF
Clock
Net Delay
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 39: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case in Figure 39a and
Figure 39b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 39a, the feedback loop is cre-
ated by routing CLK0 (or CLK2X, in Figure 39b to a global
clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case in Figure 39c and
Figure 39d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 39c, the feedback loop is
formed by feeding CLK0 (or CLK2X, in Figure 39d) back
into the FPGA using an IBUFG, which directly accesses the
global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it
exceeds the maximum permitted, divide it down to an
acceptable value using the CLKIN_DIVIDE_BY_2 attribute.
When this attribute is set to TRUE, the CLKIN frequency is
divided by a factor of two just as it enters the DCM.
Coarse Phase Shift Outputs of the DLL Compo-
nent
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted sig-
nals, respectively. These signals are described in Table 25.
Their relative timing is shown in Figure 40. For control in
finer increments than 90°, see Phase Shifter (PS).
Basic Frequency Synthesis Outputs of the DLL
Component
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also dou-
bles the frequency, but is 180° out-of-phase with respect to
CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to var-
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification