XC3S100E Datasheet, PDF (144/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
2
VCCO_2
P73
2
VCCO_2
P88
3
IO/VREF_3
P45
3
IO_L01N_3
P3
3
IO_L01P_3
P2
3
IO_L02N_3/VREF_3
P5
3
IO_L02P_3
P4
3
IO_L03N_3
P9
3
IO_L03P_3
P8
3
IO_L04N_3
P12
3
IO_L04P_3
P11
3
IO_L05N_3
P16
3
IO_L05P_3
P15
3
IO_L06N_3
P19
3
IO_L06P_3
P18
3
IO_L07N_3/LHCLK1
P23
3
IO_L07P_3/LHCLK0
P22
3
IO_L08N_3/LHCLK3
P25
3
IO_L08P_3/LHCLK2
P24
3
IO_L09N_3/LHCLK5
P29
3
IO_L09P_3/LHCLK4
P28
3
IO_L10N_3/LHCLK7
P31
3
IO_L10P_3/LHCLK6
P30
3
IO_L11N_3
P34
3
IO_L11P_3
P33
3
IO_L12N_3
P36
3
IO_L12P_3
P35
3
IO_L13N_3
P40
3
IO_L13P_3
P39
3
IO_L14N_3
P42
3
IO_L14P_3
P41
3
IO_L15N_3
P48
3
IO_L15P_3
P47
3
IO_L16N_3
P50
Type
VCCO
VCCO
VREF
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pinout Descriptions
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
3
IO_L16P_3
P49
3
IP
P6
3
IP
P14
3
IP
P26
3
IP
P32
3
IP
P43
3
IP
P51
3
IP/VREF_3
P20
3
VCCO_3
P21
3
VCCO_3
P38
3
VCCO_3
P46
GND GND
P10
GND GND
P17
GND GND
P27
GND GND
P37
GND GND
P52
GND GND
P53
GND GND
P70
GND GND
P79
GND GND
P85
GND GND
P95
GND GND
P105
GND GND
P121
GND GND
P131
GND GND
P141
GND GND
P156
GND GND
P173
GND GND
P182
GND GND
P188
GND GND
P198
GND GND
P208
VCCAUX DONE
P104
VCCAUX PROG_B
P1
VCCAUX TCK
P158
Type
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CONFIG
CONFIG
JTAG
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
23
Advance Product Specification