XC3S100E Datasheet, PDF (37/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
WEA
ENA
SSRA
CLKA
ADDRA[r_A–1:0]
DIA[w_A–p_A–1:0]
DIPA[p_A–1:0]
RAMB16_w_A_w_B
DOPA[p_A–1:0]
DOA[w_A–p_A–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[r_B–1:0]
DIB[w_B–p_B–1:0]
DIPB[p_B–1:0]
DOPB[p_B–1:0]
DOB[w_B–p_B–1:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
RAMB16_Sw
DOP[p–1:0]
DO[w–p–1:0]
(a) Dual-Port
(b) Single-Port
Notes:
DS312-2_03_021305
1. w_A and w_B are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
2. p_A and p_B are integers that indicate the number of data path lines serving as parity bits.
3. r_A and r_B are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Address Bus
ADDRA ADDRB
Data Input Bus
DIA
DIB
Parity Data
Input(s)
DIPA
DIPB
Direction
Function
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table 18.
Input
Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based
on Table 18. This selection applies to both the DI and DO paths
of a given port.
Input
Parity inputs represent additional bits included in the data input
path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See Table 18.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification