XC3S100E Datasheet, PDF (180/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Pinout Descriptions
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
FG400
Ball
J10
J12
K9
K11
L10
L12
M9
M11
Type
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
FG400
Ball
M13
N8
N10
N12
Type
VCCINT
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 30 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400 pack-
age.
Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the FG400 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
78
43
20
1
6
Right
1
74
35
12
21
6
Bottom
2
78
30
18
24
6
Left
3
74
48
12
0
6
TOTAL
304
156
62
46
24
GCLK
8
0
0
8
16
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
59
Advance Product Specification