XC3S100E Datasheet, PDF (56/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
BUFGMUX pair connects to four of the eight global clock
inputs, as shown in Figure 42. This optionally allows differ-
ential inputs to the global clock inputs without wasting a
BUFGMUX element.
The connections for the bottom-edge BUFGMUX elements
is similar to the top-edge connections.
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
BUFGMUX
pair
BUFGMUX
H
Global Clock Inputs
GCLK11 GCLK7 GCLK9 GCLK5
GCLK10 GCLK6 GCLK8 GCLK4
DCM
XC3S250E (X0Y1) ₄
XC3S500E (X0Y1)
XC3S1200E (X1Y3) 4
XC3S1600E (X1Y3)
X1Y10 X1Y11
HG
X2Y10 X2Y11 4
4
FE
DCM
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
Clock Line
in Quadrant
H
Top Left Quadrant (TL)
G
4
4
4
•
DCM
8
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
4
•
4
F
•
Top Right Quadrant (TR)
•
8
•
•
G
4
4
DCM
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
4
4
F
E
Left Spine 8 ^{Figure 44a} 8
D
Figure 44a
Horizontal Spine
8 ^{Figure 44b} 8 Right Spine
E
Figure 44b
D
•
C
4
4
8
DCM
•
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
4
4
B
•
•
C
8
4
4
•
DCM
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
4
4
•
B
4
A
Bottom Left Quadrant (BL)
Bottom Right Quadrant (BR) _A
DCM
4
XC3S250E (X0Y0) ₄
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
DC
X1Y0 X1Y1
B
A
4
DCM
XC3S100E (X0Y0)
4
XC3S250E (X1Y0)
X2Y0 X2Y1
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
GCLK2 GCLK14 GCLK0 GCLK12
GCLK3 GCLK15 GCLK1 GCLK13
Global Clock Inputs
DS312-2_04_030205
Notes:
1. Number of DCMs and locations of these DCM varies for different device densities.
2. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right
and one on the bottom right of the die.
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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Advance Product Specification