SH7137 Datasheet, PDF (942/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 22 Flash Memory
22.4.4 RAM Emulation Register (RAMER)
When the realtime programming of the user MAT is emulated, RAMER sets the area of the user
MAT which is overlapped with a part of the on-chip RAM. The RAM emulation must be executed
in user mode or in user program mode.
For the division method of the user-MAT area, see table 22.7. In order to operate the emulation
function certainly, the target MAT of the RAM emulation must not be accessed immediately after
RAMER is programmed. If it is accessed, the normal access is not guaranteed.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
- RAMS
RAM[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value
15 to 4 
All 0
3
RAMS
0
2 to 0 RAM[2:0] 000
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RAM Select
Sets whether the user MAT is emulated or not. When
RAMS = 1, all blocks of the user MAT are in the
programming/erasing protection state.
0: Emulation is not selected
Programming/erasing protection of all user-MAT
blocks is invalid
1: Emulation is selected
Programming/erasing protection of all user-MAT
blocks is valid
R/W User MAT Area Select
These bits are used with bit 3 to select the user-MAT
area to be overlapped with the on-chip RAM. (See table
22.7.)
Rev. 2.00 Sep. 10, 2008 Page 916 of 1130
REJ09B0402-0200