SH7137 Datasheet, PDF (794/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Controller Area Network (RCAN-ET)
Power On/SW Reset*¹
Reset Sequence
Configuration Mode
MCR[0] = 1
(automatically in hardware reset only)
IRR[0] = 1, GSR[3] = 1 (automatically)
clear IRR[0] Bit
Configure MCR[15]
Clear Required IMR Bits
Mailbox Setting
(STD-ID, EXT-ID, LAFM, DLC,
RTR, IDE, MBC, MBIMR, DART,
ATX, NMC, Message-Data)*²
No
GSR[3] = 0?
Yes
RCAN-ET is in Tx_Rx Mode
Set TXPR to start transmission
or stay idle to receive
Transmission_Reception
(Tx_Rx) Mode
Detect 11 recessive bits and
Join the CAN bus activity
Set Bit Timing (BCR)
Clear MCR[0]
Receive*³
Transmit*³
Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.
2. Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.
3. If there is no TXPR set, RCAN-ET will receive the next incoming message.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
Figure 19.8 Reset Sequence
Rev. 2.00 Sep. 10, 2008 Page 768 of 1130
REJ09B0402-0200