SH7137 Datasheet, PDF (252/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.4 CSn Assert Period Extension
The number of cycles from CSn assertion to RD, WRL assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WRL negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.8 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WRL are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Th
T1
T2
Tf
CK
A19 to A0
CSn
Read
RD
D7 to D0
Write
WRL
D7 to D0
Figure 9.8 CSn Assert Period Extension
Rev. 2.00 Sep. 10, 2008 Page 226 of 1130
REJ09B0402-0200