SH7137 Datasheet, PDF (545/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
12.4.3 Release from High-Impedance State
The large current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the flags in bits 12 to 15 (POE0F to POE2F, POE4F to POE6F, and POE8F) of ICSR1 to ICSR3.
However, note that when low-level sampling is selected by bits 0 to 7 in ICSR1 to ICSR3, just
writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only
after a high level is input to the POE pin and is sampled.
The large current pins that have entered high-impedance state due to output-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing the flag
in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is
ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the
large current pins. Inactive-level outputs can be obtained by setting the MTU2 and MTU2S
internal registers.
Rev. 2.00 Sep. 10, 2008 Page 519 of 1130
REJ09B0402-0200