SH7137 Datasheet, PDF (660/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
No
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Yes
Consecutive data transmission?
No
Read TEND in SSSR
No
TEND = 1?
Yes
Clear TEND to 0
[1] Initial setting:
Specify the transmit data format.
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Confirm that TEND is cleared to 0
[4]
One-bit intreval
No
elapsed?
Yes
Clear TE in SSER to 0
End transmission
Note: Hatched boxes represent SSU internal operations.
Figure 15.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)
Rev. 2.00 Sep. 10, 2008 Page 634 of 1130
REJ09B0402-0200