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| SH7137 Datasheet, PDF (1118/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 26 Electrical Characteristics
26.3.9 Synchronous Serial Communication Unit (SSU) Timing
Table 26.14 Synchronous Serial Communication Unit (SSU) Timing
Conditions: VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V, AVCC = 4.5 V to 5.5 V, AVrefh = 4.5 V to
AVCC, VSS = PLLVSS = AVSS = AVrefl = 0 V,
Ta = â20°C to +85°C (consumer applications),
Ta = â40°C to +85°C (industrial applications)
Item
Symbol Min.
Clock cycle
Master t
4
SUcyc
Slave
4
Clock high pulse width Master t
60
HI
Slave
60
Clock low pulse width
Master
tLO
60
Slave
60
Clock rise time
t

RISE
Clock fall time
t

FALL
Data input setup time
Master
tSU
30
Slave
30
Data input hold time
SCS setup time
Master
tH
10
Slave
10
Master
tLEAD
1.5
Slave
1.5
SCS hold time
Master t
1.5
LAG
Slave
1.5
Data output delay time
Master t

OD
Slave

Data output hold time
Master t
30
OH
Slave
30
Continuous transmission Master t
1.5
TD
delay time
Slave
1.5
Slave access time
tSA

Slave out release time
tREL

Note: t indicates the peripheral clock (PÏ) cycle.
pcyc
Max.
256
256




20
20








40
40




1
1
Unit
t
pcyc
ns
ns
ns
ns
ns
ns
tpcyc
t
pcyc
ns
ns
t
pcyc
tpcyc
tpcyc
Reference
Figure
Figures 26.23 to
26.26
Figures 26.25,
26.26
Rev. 2.00 Sep. 10, 2008 Page 1092 of 1130
REJ09B0402-0200
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