SH7137 Datasheet, PDF (120/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
Input
control
UBC
WDT
CMT
MTU2
A/D
SCI
MTU2S
POE
SSU
RCAN-ET
I²C2
DTC
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTCERA to
DTCERE
ICR0
IRQCR
IRQSR
IPR
IPRA, IPRD to IPRF,
IPRH to IPRM
[Legend]
UBC: User break controller
WDT: Watchdog timer
CMT: Compare match timer
SCI:
Serial communication interface
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2S
A/D:
A/D converter
POE: Port output enable
DTC: Data transfer controller
SSU: Synchronous serial communication unit
RCAN-ET:Controller area network
I²C2:
I²C bus interface 2
Module bus
INTC
Bus
interface
ICR0:
Interrupt control register 0
IRQCR:
IRQ control register
IRQSR:
IRQ status register
IPRA, IPRD to IPRF,
IPRH to IPRM:
Interrupt priority registers A, D to F, and H to M
SR:
Status register
DTCERA to DTCERE: DTC enable registers A to E
Figure 6.1 Block Diagram of INTC
Rev. 2.00 Sep. 10, 2008 Page 94 of 1130
REJ09B0402-0200