SH7137 Datasheet, PDF (740/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 Compare Match Timer (CMT)
18.2 Register Descriptions
The CMT has the following registers. For details on register addresses and register states during
each processing, refer to section 25, List of Registers. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name.
Table 18.1 Register Configuration
Register Name
Compare match timer start
register
Compare match timer
control/status register_1
Compare match counter_0
Compare match constant
register_0
Compare match timer
control/status register_0
Compare match counter_1
Compare match constant
register_1
Abbrevia-
tion
R/W Initial Value Address
Access
Size
CMSTR R/W H'0000
H'FFFFCE00 8, 16, 32
CMCSR_0 R/W H'0000
H'FFFFCE02 8, 16
CMCNT_0 R/W H'0000
CMCOR_0 R/W H'FFFF
H'FFFFCE04 8, 16, 32
H'FFFFCE06 8, 16
CMCSR_1 R/W H'0000
H'FFFFCE08 8, 16, 32
CMCNT_1 R/W H'0000
CMCOR_1 R/W H'FFFF
H'FFFFCE0A 8, 16
H'FFFFCE0C 8, 16, 32
Rev. 2.00 Sep. 10, 2008 Page 714 of 1130
REJ09B0402-0200