SH7137 Datasheet, PDF (1041/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 25 List of Registers
Register Name
Flash MAT select register
Flash transfer destination address
register
DTC enable register A
DTC enable register B
DTC enable register C
DTC enable register D
DTC enable register E
DTC control register
DTC vector base register
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
NF2CYC register
SS control register H
SS control register L
SS mode register
SS enable register
SS status register
SS control register 2
SS transmit data register 0
SS transmit data register 1
SS transmit data register 2
SS transmit data register 3
SS receive data register 0
SS receive data register 1
No. of
Abbreviation Bits Address
Module
Connected
Access Size No. of Access Cycles Bus Width
FMATS
8
H'FFFFCC05 FLASH 8
Pφ (reference clock)
16 bits
FTDAR
8
H'FFFFCC06
8
B: 5
DTCERA
16
H'FFFFCC80 DTC
DTCERB
16
H'FFFFCC82
DTCERC
16
H'FFFFCC84
DTCERD
16
H'FFFFCC86
DTCERE
16
H'FFFFCC88
DTCCR
8
H'FFFFCC90
DTCVBR
32
H'FFFFCC94
ICCR1
8
H'FFFFCD80 I²C2
ICCR2
8
H'FFFFCD81
ICMR
8
H'FFFFCD82
ICIER
8
H'FFFFCD83
ICSR
8
H'FFFFCD84
SAR
8
H'FFFFCD85
ICDRT
8
H'FFFFCD86
ICDRR
8
H'FFFFCD87
NF2CYC
8
H'FFFFCD88
SSCRH
8
H'FFFFCD00 SSU
SSCRL
8
H'FFFFCD01
SSMR
8
H'FFFFCD02
SSER
8
H'FFFFCD03
SSSR
8
H'FFFFCD04
SSCR2
8
H'FFFFCD05
SSTDR0
8
H'FFFFCD06
SSTDR1
8
H'FFFFCD07
SSTDR2
8
H'FFFFCD08
SSTDR3
8
H'FFFFCD09 SSU
SSRDR0
8
H'FFFFCD0A
SSRDR1
8
H'FFFFCD0B
8, 16
8, 16
8, 16
8, 16
8, 16
8
8, 16, 32
8
8
8
8
8
8
8
8
8
8, 16
8
8, 16
8
8, 16
8
8, 16
8
8, 16
8
8, 16
8
Pφ (reference clock)
B: 2
W: 2
L: 4
Pφ reference
B: 2
Pφ (reference clock)
B: 2
W: 2
Pφ (reference clock)
B: 2
W: 2
16 bits
8 bits
16 bits
16 bits
Rev. 2.00 Sep. 10, 2008 Page 1015 of 1130
REJ09B0402-0200