SH7137 Datasheet, PDF (784/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Controller Area Network (RCAN-ET)
(1) Transmit Pending Register (TXPR1, TXPR0)
The concatenation of TXPR1 and TXPR0 is a 32-bit register that contains any transmit pending
flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as
two consecutive word accesses.
<Longword Write Operation>
<upper word write>
16-bit Peripheral bus
<lower word write>
16-bit Peripheral bus
Temp
consecutive access
Temp
TXPR1
H'020
TXPR0
H'022
Data is stored into Temp instead of TXPR1.
<Longword Read Operation>
<upper word read>
16-bit Peripheral bus
TXPR1
H'020
TXPR0
H'022
Lower word data are stored into TXPR0.
TXPR1 is always H'0000.
<lower word read>
16-bit Peripheral bus
always
H'0000
Temp
consecutive access
Temp
TXPR1
H'020
TXPR0
H'022
TXPR0 is stored into Temp,
when TXPR1 (= H'0000) is read.
TXPR1
H'020
TXPR0
H'022
Temp is read instead of TXPR0.
The TXPR1 register cannot be modified and it is always fixed to '0'. The TXPR0 controls
Mailbox-15 to Mailbox-1. The CPU may set the TXPR bits to affect any message being
considered for transmission by writing a '1' to the corresponding bit location. Writing a '0' has no
effect, and TXPR cannot be cleared by writing a '0' and must be cleared by setting the
corresponding TXCR bits. TXPR may be read by the CPU to determine which, if any,
transmissions are pending or in progress. In effect there is a transmit pending bit for all Mailboxes
except for the Mailbox-0. Writing a '1' to a bit location when the mailbox is not configured to
transmit is not allowed.
Rev. 2.00 Sep. 10, 2008 Page 758 of 1130
REJ09B0402-0200