SH7137 Datasheet, PDF (241/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
12, 11 SW[1:0] 00
R/W Number of Delay Cycles from Address and CSn
Assertion to RD and WRL Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WRL assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles
Specify the number of wait cycles required for read
access.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycles is 0.
0: External wait input is valid
1: External wait input is ignored
Rev. 2.00 Sep. 10, 2008 Page 215 of 1130
REJ09B0402-0200