SH7137 Datasheet, PDF (211/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

SAR
Section 8 Data Transfer Controller (DTC)
Transfer source data area
Transfer destination data area
(specified as block area)
1st block
:
:
:
Nth block
Transfer
Block area
DAR
Figure 8.8 Memory Map in Block Transfer Mode
(When Transfer Destination is Specified as Block Area)
8.5.6 Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB
set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB,
MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the
chain transfer operation.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source
flag for the activation source and DTCER are not affected.
In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB
to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.
Rev. 2.00 Sep. 10, 2008 Page 185 of 1130
REJ09B0402-0200