SH7137 Datasheet, PDF (172/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.4.3 Break on Data Access Cycle
1. If the L bus is specified as a break condition for data access break, condition comparison is
performed for the address (and data) accessed by the executed instructions, and a user break is
generated if the condition is satisfied. If the I bus is specified as a break condition, condition
comparison is performed for the addresses (and data) of the data access cycles that are issued
on the I bus by all bus masters including the CPU, and a user break is generated if the
condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section
7.4.1, Flow of the User Break Operation.
2. The relationship between the data access cycle address and the comparison condition for each
operand size is listed in table 7.3.
Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Longword
Word
Byte
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BARA or
BARB), for example, the bus cycle in which the break condition is satisfied is as follows
(where other conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. When the data value is included in the break conditions:
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle register (BBRA or BBRB). When data
values are included in break conditions, a user break is generated when the address conditions
and data conditions both match. To specify byte data for this case, set the same data in two
bytes at bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data
mask register (BDMRA or BDMRB). When word or byte is set, bits 31 to 16 of BDRA or
BDRB and BDMRA or BDMRB are ignored.
4. If the L bus is selected, a user break is generated on ending execution of the instruction that
matches the break condition, and immediately before the next instruction is executed.
However, when data is also specified as the break condition, the break may occur on ending
execution of the instruction following the instruction that matches the break condition. When
the I bus is selected, the instruction at which the user break is generated cannot be determined.
Rev. 2.00 Sep. 10, 2008 Page 146 of 1130
REJ09B0402-0200