SH7137 Datasheet, PDF (555/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Watchdog Timer (WDT)
13.3.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 13.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
15
Address: H'FFFFE810
87
0
H'5A
Write data
WTCSR write
15
Address: H'FFFFE812
87
0
H'A5
Write data
Figure 13.2 Writing to WTCNT and WTCSR
Rev. 2.00 Sep. 10, 2008 Page 529 of 1130
REJ09B0402-0200