SH7137 Datasheet, PDF (643/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.3 Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 15.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 15.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 15.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 15.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 15.3 (5) and (6)).
Rev. 2.00 Sep. 10, 2008 Page 617 of 1130
REJ09B0402-0200