SH7137 Datasheet, PDF (633/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Initial
Bit
Bit Name Value R/W
4, 3 
All 0
R
2 to 0 CKS[2:0] 000
R/W
Section 15 Synchronous Serial Communication Unit (SSU)
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
15.3.4 SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit: 7
6
5
TE RE
-
Initial value: 0
0
0
R/W: R/W R/W R
4
3
2
1
0
-
TEIE TIE RIE CEIE
0
0
0
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
TE
0
R/W
6
RE
0
R/W
5, 4 
All 0
R
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 10, 2008 Page 607 of 1130
REJ09B0402-0200