SH7137 Datasheet, PDF (238/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
26, 25 IWRWD[1:0] 11
R/W
24

0
R
23, 22 IWRWS[1:0] 11
R/W
21

0
R
20, 19 IWRRD[1:0] 11
R/W
Description
Specification for Idle Cycles between Read-Write
Cycles in Different Spaces
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-write cycles in
different spaces.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Write
Cycles in the Same Space
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-write cycles in the
same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Read
Cycles in Different Spaces
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-read cycles in
different spaces.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Rev. 2.00 Sep. 10, 2008 Page 212 of 1130
REJ09B0402-0200