SH7137 Datasheet, PDF (247/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.2 Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of
the fact that mainly SRAM without a byte selection will be directly connected. Figure 9.2 shows
the basic timings of normal space access. A no-wait normal access is completed in two cycles.
T1
T2
CK
A19 to A0
CSn
Read
RD
D7 to D0
Write
WRL
D7 to D0
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
It is necessary to control of outputing the data that has been read using RD when a buffer is
established in the data bus.
Figures 9.3 and 9.4 show the basic timings of continuous accesses to normal space. If the WM bit
in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.3). If
the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.4).
Rev. 2.00 Sep. 10, 2008 Page 221 of 1130
REJ09B0402-0200