SH7137 Datasheet, PDF (1149/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Index
A
A/D conversion time............................... 704
A/D converter (ADC) ............................. 685
A/D converter activation......................... 422
A/D converter activation by MTU2 and
MTU2S ................................................... 705
A/D converter characteristics................ 1101
A/D converter start request delaying
function................................................... 405
Absolute accuracy................................... 709
Absolute maximum ratings................... 1063
AC bus timing....................................... 1078
AC characteristics................................. 1071
AC characteristics measurement
conditions ............................................. 1100
Access in view of LSI internal bus
master ..................................................... 234
Access size and data alignment .............. 220
Access wait control................................. 224
Address error .............................. 81, 90, 988
Address map ........................................... 205
Address map for each mailbox ............... 729
Address map for the operating modes ...... 52
Addressing modes..................................... 26
Arithmetic operation instructions ............. 39
Asynchronous mode ....................... 533, 566
B
Bit synchronous circuit ........................... 681
Block transfer mode................................ 184
Boot mode .............................................. 918
Branch instructions ................................... 43
Break comparison conditions ................. 121
Break detection and processing .............. 595
Break on data access cycle ..................... 146
Bus arbitration ........................................ 230
Bus clock (Bφ) .......................................... 55
Bus release state........................................ 47
Bus state controller (BSC) ...................... 203
C
Calculating exception handling vector
table addresses .......................................... 78
CAN interface ......................................... 727
Chain transfer.......................................... 185
Changing frequency .................................. 69
Clock (MIφ) for the MTU2S module ........ 55
Clock (MPφ) for the MTU2 module ......... 55
Clock frequency control circuit................. 57
Clock operating mode ............................... 60
Clock pulse generator (CPG) .................... 55
Clock synchronous mode ................ 533, 576
Clock synchronous serial format
(I²C2) ...................................................... 670
Clock timing ......................................... 1072
CMT interrupt sources ............................ 719
Compare match timer (CMT) ................. 713
Complementary PWM mode .................. 361
Conflict between NMI interrupt and
DTC activation........................................ 200
Connecting crystal resonator..................... 70
Continuous scan mode ............................ 701
Control signal timing ............................ 1075
Controller area network (RCAN-ET)...... 723
CPU........................................................... 17
Crystal oscillator ....................................... 57
CSn assert period extension .................... 226
D
Data transfer controller (DTC)................ 157
Data transfer instructions .......................... 37
Rev. 2.00 Sep. 10, 2008 Page 1123 of 1130
REJ09B0402-0200