SH7137 Datasheet, PDF (209/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
Table 8.7 Register Function in Repeat Transfer Mode
Written Back Value
Register Function
CRAL is not 1
CRAL is 1
SAR
Source address
Incremented/decremented/fixed* DTS = 0: Incremented/
decremented/fixed*
DTS = 1: SAR initial value
DAR
Destination address Incremented/decremented/fixed* DTS = 0: DAR initial value
DTS = 1: Incremented/
decremented/fixed*
CRAH Transfer count
storage
CRAH
CRAH
CRAL Transfer count A CRAL − 1
CRAH
CRB
Transfer count B Not updated
Not updated
Note: * Transfer information writeback is skipped.
Transfer source data area
(specified as repeat area)
Transfer destination data area
SAR
Transfer
DAR
Figure 8.7 Memory Map in Repeat Transfer Mode
(When Transfer Source is Specified as Repeat Area)
Rev. 2.00 Sep. 10, 2008 Page 183 of 1130
REJ09B0402-0200