SH7137 Datasheet, PDF (746/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 Compare Match Timer (CMT)
18.5 Usage Notes
18.5.1 Module Standby Mode Setting
The CMT operation can be disabled or enabled using the standby control register. The initial
setting is for CMT operation to be halted. Access to a register is enabled by clearing module
standby mode. For details, refer to section 24, Power-Down Modes.
18.5.2 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 18.5 shows
the timing to clear the CMCNT counter.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
Counter clear
CMCNT
N
H'0000
Figure 18.5 Conflict between Write and Compare-Match Processes of CMCNT
Rev. 2.00 Sep. 10, 2008 Page 720 of 1130
REJ09B0402-0200