SH7137 Datasheet, PDF (532/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
1, 0 POE4M[1:0] 00
R/W*² POE4 mode 1 and 0
These bits select the input mode of the POE4 pin.
00: Accept request on falling edge of POE4 input
01: Accept request when POE4 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE4 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE4 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
12.3.4 Output Level Control/Status Register 2 (OCSR2)
OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OSF2 -
-
-
-
- OCE2 OIE2 -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:R/(W)*¹ R
R
R
R
R R/W*² R/W R
R
R
R
R
R
R
R
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Initial
Bit
Bit Name value R/W Description
15
OSF2
0
R/(W)*¹ Output Short Flag 2
This flag indicates that any one of the three pairs of
MTU2S 2-phase outputs to be compared has
simultaneously become an active level.
[Clearing condition]
• By writing 0 to OSF2 after reading OSF2 = 1
[Setting condition]
• When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
Rev. 2.00 Sep. 10, 2008 Page 506 of 1130
REJ09B0402-0200