SH7137 Datasheet, PDF (11/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

5.5.2 Trap Instructions ..................................................................................................... 85
5.5.3 Illegal Slot Instructions ........................................................................................... 86
5.5.4 General Illegal Instructions..................................................................................... 86
5.6 Cases when Exceptions are Accepted .................................................................................. 87
5.7 Stack States after Exception Handling Ends ........................................................................ 88
5.8 Usage Notes ......................................................................................................................... 90
5.8.1 Value of Stack Pointer (SP) .................................................................................... 90
5.8.2 Value of Vector Base Register (VBR) .................................................................... 90
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 90
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 91
Section 6 Interrupt Controller (INTC) .................................................................93
6.1 Features................................................................................................................................ 93
6.2 Input/Output Pins ................................................................................................................. 95
6.3 Register Descriptions ........................................................................................................... 96
6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 97
6.3.2 IRQ Control Register (IRQCR) .............................................................................. 98
6.3.3 IRQ Status register (IRQSR) ................................................................................ 100
6.3.4 Interrupt Priority Registers A, D to F, and H to M
(IPRA, IPRD to IPRF, and IPRH to IPRM).......................................................... 103
6.4 Interrupt Sources................................................................................................................ 106
6.4.1 External Interrupts ................................................................................................ 106
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 107
6.4.3 User Break Interrupt ............................................................................................. 107
6.5 Interrupt Exception Handling Vector Table....................................................................... 108
6.6 Interrupt Operation............................................................................................................. 112
6.6.1 Interrupt Sequence ................................................................................................ 112
6.6.2 Stack after Interrupt Exception Handling ............................................................. 115
6.7 Interrupt Response Time.................................................................................................... 115
6.8 Data Transfer with Interrupt Request Signals .................................................................... 117
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation
and CPU Interrupts ............................................................................................... 118
6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation,
but Not CPU Interrupts ......................................................................................... 118
6.8.3 Handling Interrupt Request Signals as Sources for CPU Interrupts,
but Not DTC Activation........................................................................................ 119
6.9 Usage Note......................................................................................................................... 119
Rev. 2.00 Sep. 10, 2008 Page xi of xxvi