SH7137 Datasheet, PDF (553/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Watchdog Timer (WDT)
13.3.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal
reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the
RES pin.
When used to count the clock settling time for revoking a software standby, it retains its value
after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a
byte access to read WTCSR.
Note: WTCSR differs from other registers in that it is more difficult to write to. See section
13.3.3, Notes on Register Access, for details.
Bit: 7
TME
Initial value: 0
R/W: R/W
6
5
4
3
WT/IT RSTS WOVF IOVF
0
0
0
0
R/W R/W R/W R/W
2
1
0
CKS[2:0]
0
0
0
R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
TME
0
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0 when
using the WDT to revoke software standby mode.
0: Timer disabled: Count-up stops and WTCNT value is
retained
1: Timer enabled
6
WT/IT
0
R/W Timer Mode Select
Selects whether to use the WDT as a watchdog timer or
an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Note: If WT/IT is modified when the WDT is operating,
the up-count may not be performed correctly.
Rev. 2.00 Sep. 10, 2008 Page 527 of 1130
REJ09B0402-0200