English
Language : 

SH7137 Datasheet, PDF (203/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family
◁
Section 8 Data Transfer Controller (DTC)
Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included)
1st Transfer
2nd Transfer
Transfer
Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*1 CHNE CHNS RCHNE DISEL Counter*1 DTC Transfer
Normal 0


0
Not 0





Ends at 1st
transfer
0


0
0
0


1











Ends at 1st
transfer
Interrupt request
to CPU
1
0



0


0
Not 0
Ends at 2nd
transfer
0


0
0
0


1

Ends at 2nd
transfer
Interrupt request
to CPU
1
1

0
Not 0





Ends at 1st
transfer
1
1

1
Not 0





Ends at 1st
transfer
Interrupt request
to CPU
1
1


0
0


0
Not 0
Ends at 2nd
transfer
0


0
0
0


1

Ends at 2nd
transfer
Interrupt request
to CPU
Rev. 2.00 Sep. 10, 2008 Page 177 of 1130
REJ09B0402-0200
 ▷