SH7137 Datasheet, PDF (22/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Pin Function Controller (PFC) ........................................................ 785
20.1 Register Descriptions......................................................................................................... 803
20.1.1 Port A I/O Register L (PAIORL).......................................................................... 804
20.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).................................. 804
20.1.3 Port B I/O Register L (PBIORL) .......................................................................... 819
20.1.4 Port B Control Registers L1, L2 (PBCRL1, PBCRL2) ........................................ 819
20.1.5 Port D I/O Register L (PDIORL) (SH7137 Only) ................................................ 827
20.1.6 Port D Control Registers L1 to L3 (PDCRL1 to PDCRL3) (SH7137 Only) ........ 828
20.1.7 Port E I/O Registers L, H (PEIORL, PEIORH).................................................... 833
20.1.8 Port E Control Registers L1 to L4, H1, H2
(PECRL1 to PECRL4, PECRH1, PECRH2) ........................................................ 834
20.1.9 IRQOUT Function Control Register (IFCR) ........................................................ 851
20.2 Usage Notes ....................................................................................................................... 852
Section 21 I/O Ports........................................................................................... 853
21.1 Port A................................................................................................................................. 854
21.1.1 Register Descriptions............................................................................................ 856
21.1.2 Port A Data Register L (PADRL)......................................................................... 856
21.1.3 Port A Port Register L (PAPRL) .......................................................................... 858
21.2 Port B ................................................................................................................................. 859
21.2.1 Register Descriptions............................................................................................ 860
21.2.2 Port B Data Register L (PBDRL) ......................................................................... 860
21.2.3 Port B Port Register L (PBPRL)........................................................................... 863
21.3 Port D (SH7137 Only) ....................................................................................................... 865
21.3.1 Register Descriptions............................................................................................ 865
21.3.2 Port D Data Register L (PDDRL)......................................................................... 866
21.3.3 Port D Port Register L (PDPRL) .......................................................................... 867
21.4 Port E ................................................................................................................................. 869
21.4.1 Register Descriptions............................................................................................ 871
21.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ......................................... 871
21.4.3 Port E Port Registers H and L (PEPRH and PEPRL) ........................................... 874
21.5 Port F ................................................................................................................................. 876
21.5.1 Register Descriptions............................................................................................ 877
21.5.2 Port F Data Register L (PFDRL) .......................................................................... 878
Section 22 Flash Memory.................................................................................. 881
22.1 Features.............................................................................................................................. 881
22.2 Overview............................................................................................................................ 883
22.2.1 Block Diagram...................................................................................................... 883
Rev. 2.00 Sep. 10, 2008 Page xxii of xxvi