SH7137 Datasheet, PDF (1101/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 26 Electrical Characteristics
26.3.2 Control Signal Timing
Table 26.7 Control Signal Timing
Conditions: V_CC = 3.0 V to 3.6 V or 4.0 V to 5.5 V, AV_CC = 4.5 V to 5.5 V,
AV_refh = 4.5 V to AV_CC, V_SS = PLLV_SS = AV_SS = AV_refl = 0 V,
T_a = –20°C to +85°C (consumer applications),
T_a = –40°C to +85°C (industrial applications)
Item
Symbol Min.
Max.
Unit Reference Figure
RES pulse width
t_RESW
20*²

t *4
Bcyc
Figures 26.3, 26.4,
RES setup time*¹
t_RESS
65

ns
26.6, 26.7
RES hold time
t_RESH
15

ns
MRES pulse width
t_MRESW
20*³

t *4
Bcyc
MRES setup time*¹
t_MRESS
25

ns
MRES hold time
t_MRESH
15

ns
MD1, MD0, FWE setup time
t_MDS
20

t *4
Bcyc
Figure 26.6
BREQ setup time
BREQ hold time
t_BREQS
t_BREQH
1/2t_Bcyc + 15 
1/2t_Bcyc + 10 
ns
Figure 26.9
ns
NMI setup time*¹
t_NMIS
60

ns
Figure 26.7
NMI hold time
t_NMIH
10

ns
IRQ3 to IRQ0 setup time*¹
t_IRQS
35

ns
IRQ3 to IRQ0 hold time
t_IRQH
35

ns
IRQOUT output delay time
t_IRQOD

100
ns
Figure 26.8
BACK delay time
t_BACKD

1/2t_Bcyc + 20 ns
Figures 26.9, 26.10
Bus tri-state delay time
t_BOFF
0
100
ns
Bus buffer on time
t_BON
0
100
ns
Notes: 1. The RES, MRES, NMI, BREQ, and IRQ3 to IRQ0 signals are asynchronous signals.
When the setup time is satisfied, change of signal level is detected at the rising edge of
the clock. If not, the detection is delayed until the next rising edge of the clock.
2. In standby mode, t_RESW = t_OSC2 (10 ms).
3. In standby mode, t = t (10 ms).
MRESW
OSC2
4. t indicates external bus clock cycle time (Bφ = CK).
Bcyc
Rev. 2.00 Sep. 10, 2008 Page 1075 of 1130
REJ09B0402-0200