SH7137 Datasheet, PDF (465/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the
compare match signal is also generated.
Figure 10.122 shows the timing in this case.
MPφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 10.122 Contention between TGR Write and Compare Match
Rev. 2.00 Sep. 10, 2008 Page 439 of 1130
REJ09B0402-0200