SH7137 Datasheet, PDF (184/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
INTC
On-chip
memory
On-chip
peripheral
module
Interrupt
request
CPU interrupt
request
Interrupt source
clear request
DTC
Register
control
Activation
control
CPU/DTC
request
determination
Interrupt
control
MRA
MRB
SAR
DAR
CRA
CRB
DTCERA to
DTCERE
DTCCR
DTCVBR
External
memory
Bus interface
External device
(memory mapped)
Bus state
controller
[Legend]
MRA, MRB:
DTC mode registers A, B
SAR:
DTC source address register
DAR:
DTC destination address register
CRA, CRB:
DTC transfer count registers A, B
DTCERA to DTCERE: DTC enable registers A to E
DTCCR:
DTC control register
DTCVBR:
DTC vector base register
Figure 8.1 Block Diagram of DTC
Rev. 2.00 Sep. 10, 2008 Page 158 of 1130
REJ09B0402-0200