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SH7137 Datasheet, PDF (198/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family
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Section 8 Data Transfer Controller (DTC)
Table 8.2 shows correspondence between the DTC activation source and vector address.
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
External pin
MTU2_0
MTU2_1
MTU2_2
MTU2_3
MTU2_4
MTU2_5
Activation
Source
IRQ0
IRQ1
IRQ2
IRQ3
TGIA_0
TGIB_0
TGIC_0
TGID_0
TGIA_1
TGIB_1
TGIA_2
TGIB_2
TGIA_3
TGIB_3
TGIC_3
TGID_3
TGIA_4
TGIB_4
TGIC_4
TGID_4
TCIV_4
TGIU_5
TGIV_5
TGIW_5
DTC Vector
Vector Address
Number Offset
DTCE*1
64
H'500
DTCERA15
65
H'504
DTCERA14
66
H'508
DTCERA13
67
H'50C
DTCERA12
88
H'560
DTCERB15
89
H'564
DTCERB14
90
H'568
DTCERB13
91
H'56C
DTCERB12
96
H'580
DTCERB11
97
H'584
DTCERB10
104
H'5A0
DTCERB9
105
H'5A4
DTCERB8
112
H'5C0
DTCERB7
113
H'5C4
DTCERB6
114
H'5C8
DTCERB5
115
H'5CC
DTCERB4
120
H'5E0
DTCERB3
121
H'5E4
DTCERB2
122
H'5E8
DTCERB1
123
H'5EC
DTCERB0
124
H'5F0
DTCERC15
128
H'600
DTCERC14
129
H'604
DTCERC13
130
H'608
DTCERC12
Transfer
Source
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Transfer
Destination Priority
Arbitrary*2 High
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2 Low
Rev. 2.00 Sep. 10, 2008 Page 172 of 1130
REJ09B0402-0200
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