SH7137 Datasheet, PDF (731/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 A/D Converter (ADC)
TRGAN
(MTU2, MTU2S trigger signal)
ADST
tD
Sampling and
hold time (tSPLSH)
A/D conversion time (tCONV)
tOFC
Sampling and
hold time (tSPL)
A/D
converter
ADDR
Waiting
Sample-
and-hold*¹
OFC
Sample-
and-hold*²
A/D conversion
ADF
Notes: 1. Sample-and-hold circuit for GrA and GrB
2. Sample-and-hold circuit common to all channels
Conversion time
per channel
50 states
Pφ = 32 MHz: 1.56 µs
Pφ = 40MHz: 1.25 µs
Figure 17.5 A/D Conversion Timing (Single-Cycle Scan Mode)
Waiting
End of A/D
conversion
17.4.4 A/D Converter Activation by MTU2 and MTU2S
A/D conversion is activated by the A/D conversion start triggers (TRGAN, TRG0N, TRG4N, and
TRG4BN) from the MTU2 and A/D conversion start triggers (TRGAN, TRG4AN, and TRG4BN)
from the MTU2S. To enable this function, set the TRGE bit in ADCR to 1 and clear the EXTRG
bit to 0. After this setting is made, if an A/D conversion start trigger from the MTU2 or MTU2S is
generated, the ADST bit is set to 1. The timing between the setting of the ADST bit and the start
of the A/D conversion is the same for all A/D conversion activation soures.
The A/D conversion start trigger must be input after ADCR, ADSTRGR, and ADANSR registers
have been set.
Rev. 2.00 Sep. 10, 2008 Page 705 of 1130
REJ09B0402-0200