SH7137 Datasheet, PDF (789/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Controller Area Network (RCAN-ET)
• RXPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a '1' to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 15 to 0 respectively.
Bit[15:0]: RXPR0
0
1
Description
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox received a CAN Data Frame
[Setting Condition] Completion of Data Frame receive on corresponding
mailbox
(6) Remote Frame Receive Pending Register (RFPR0)
The RFPR0 is a 16-bit read / conditionally-write registers. The RFPR is a register that contains the
received Remote Frame pending flags associated with the configured Receive Mailboxes. When a
CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the
mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a
RFPR bit is set, it also sets IRR2 (Remote Frame Request Interrupt Flag) if its MBIMR (Mailbox
Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please
note that these bits are only set by receiving Remote Frames and not by receiving Data frames.
• RFPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RFPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a '1' to clear.
Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.
Rev. 2.00 Sep. 10, 2008 Page 763 of 1130
REJ09B0402-0200