SH7137 Datasheet, PDF (1019/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Bit
6 to 0
Section 24 Power-Down Modes
Bit Name

Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
24.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP
7
6
-
MSTP
4
-
-
-
-
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R/W R R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7
MSTP7
0
R/W Module Stop Bit 7
When this bit is set to 1, the clock supply to the RAM is
halted.
0: RAM operates
1: Clock supply to RAM halted
6
MSTP6
0
R/W Module Stop Bit 6
When this bit is set to 1, the clock supply to the ROM is
halted.
0: ROM operates
1: Clock supply to ROM halted
5

1
R Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 2.00 Sep. 10, 2008 Page 993 of 1130
REJ09B0402-0200