SH7137 Datasheet, PDF (141/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
6.6.2 Stack after Interrupt Exception Handling
Figure 6.4 shows the stack after interrupt exception handling.
Address
4n – 8
4n – 4
4n
PC^*1
SR
32 bits
32 bits
SP^*2
Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed
instruction.
2. Always make sure that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Handling
6.7 Interrupt Response Time
Table 6.4 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction of the
interrupt handling routine begins.
Rev. 2.00 Sep. 10, 2008 Page 115 of 1130
REJ09B0402-0200