SH7137 Datasheet, PDF (751/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Controller Area Network (RCAN-ET)
19.2 Architecture
The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN
frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed
from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox,
Mailbox Control and CAN Interface. The figure below shows the block diagram of the RCAN-ET
Module. The bus interface timing is designed according to the peripheral bus I/F required for each
product.
CAN Interface
REC
CRx0
CTx0
Can Core
TEC
BCR
Transmit Buffer
Receive Buffer
Control
Signals
Status
Signals
clkp
preset_n
pms_can_n
p_read_n
p_write_n
psize_n
pwait_can_n
pa
pd
IrQs
scan_mode
16-bit
peripheral
bus
Micro Processor
Interface
MCR
IRR
GSR
IMR
TXPR
TXCR
RXPR
MBIMR
TXACK
ABACK
RFPR
UMSR
Mailbox Control
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox 0 - 15 (RAM)
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox 0 - 15 (register)
Figure 19.1 RCAN-ET Architecture
control0
LAFM
DATA
control1
Rev. 2.00 Sep. 10, 2008 Page 725 of 1130
REJ09B0402-0200