SH7137 Datasheet, PDF (460/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figures 10.115 and 10.116
show the timing for status flag clearing by the CPU, and figures 10.117 and 10.118 show the
timing for status flag clearing by the DTC.
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.116 Timing for Status Flag Clearing by CPU (Channel 5)
Rev. 2.00 Sep. 10, 2008 Page 434 of 1130
REJ09B0402-0200