SH7137 Datasheet, PDF (717/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 A/D Converter (ADC)
Initial
Bit Bit Name Value
4
ADIE
0
3, 2 
All 0
1
TRGE
0
R/W Description
R/W A/D Interrupt Enable
Enables or disables the generation of A/D conversion end
interrupts (ADI_3 and ADI_4) to the CPU. Operating
modes must be changed when the ADST bit is 0 to
prevent incorrect operations.
When A/D conversion ends and the ADF bit in ADSR is
set to 1 and this bit is set to 1, ADI_3 or ADI_4 is sent to
the CPU. By clearing the ADF bit or the ADIE bit to 0,
ADI_3 and ADI_4 can be cleared.
0: Generation of A/D conversion end interrupt is disabled
1: Generation of A/D conversion end interrupt is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Trigger Enable
Enables or disables A/D conversion start by the external
trigger input (ADTRG) or A/D conversion start triggers
from the MTU2 and MTU2S (TRGAN, TRG0N, TRG4AN,
and TRG4BN from the MTU2 and TRGAN, TRG4AN, and
TRG4BN from the MTU2S). For selection of the external
trigger and A/D conversion start trigger from the MTU2 or
MTU2S, see the description of the EXTRG bit.
0: A/D conversion start by the external trigger or an A/D
conversion start trigger from the MTU or MTU2S is
disabled
1: A/D conversion start by the external trigger or an A/D
conversion start trigger from the MTU2 or MTU2S is
enabled
Rev. 2.00 Sep. 10, 2008 Page 691 of 1130
REJ09B0402-0200