SH7137 Datasheet, PDF (531/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
8
PIE2
0
R/W Port Interrupt Enable 2
This bit enables/disables interrupt requests when any one
of the POE4F to POE6F bits of the ICSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7, 6 
All 0 R
Reserved
5, 4 POE6M[1:0] 00
R/W*²
These bits are always read as 0. The write value should
always be 0.
POE6 mode 1 and 0
These bits select the input mode of the POE6 pin.
00: Accept request on falling edge of POE6 input
01: Accept request when POE6 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE6 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
3, 2 POE5M[1:0] 00
R/W*²
11: Accept request when POE6 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
POE5 mode 1 and 0
These bits select the input mode of the POE5 pin.
00: Accept request on falling edge of POE5 input
01: Accept request when POE5 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE5 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE5 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
Rev. 2.00 Sep. 10, 2008 Page 505 of 1130
REJ09B0402-0200