SH7137 Datasheet, PDF (1023/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Bit
3
2 to 0
Section 24 Power-Down Modes
Bit Name
MSTP19
Initial
Value
1

All 1
R/W Description
R/W Module Stop Bit 19
When this bit is set to 1, the clock supply to the A/D_0
is halted.
0: A/D_0 operates
1: Clock supply to A/D_0 halted
R Reserved
These bits are always read as 1. The write value should
always be 1.
24.3.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
MSTP MSTP
25
24
Initial value: 0
0
0
0
0
0
1
1
R/W: R
R
R
R
R
R R/W R/W
Bit
7 to 2
1
0
Bit Name

Initial
Value
All 0
MSTP25 1
MSTP24 1
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Module Stop Bit 25
When this bit is set to 1, the clock supply to the AUD is
halted.
0: AUD operates
1: Clock supply to AUD halted
R/W Module Stop Bit 24
When this bit is set to 1, the clock supply to the UBC is
halted.
0: UBC operates
1: Clock supply to UBC halted
Rev. 2.00 Sep. 10, 2008 Page 997 of 1130
REJ09B0402-0200