SH7137 Datasheet, PDF (711/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 A/D Converter (ADC)
Section 17 A/D Converter (ADC)
This LSI includes a successive approximation type 12-bit A/D converter.
17.1 Features
• 12-bit resolution
• Input channels
12 channels for the SH7136 (two independent A/D conversion modules)
16 channels for the SH7137 (two independent A/D conversion modules)
• Fast A/D conversion
When operating at Pφ = 40 MHz, conversion time is 1.25 µs per channel (A/D clock = 40 MHz
and conversion done in 50 states)
• Two operating modes
 Single-cycle scan mode: Continuous A/D conversion on one to eight channels
 Continuous scan mode: Repetitive A/D conversion on one to eight channels
• 12-bit A/D data registers
The SH7136 has four registers for A/D_0 and eight registers for A/D_1, which makes a total of
twelve 16-bit A/D data registers (ADDR). The SH7137 has eight registers for both A/D_0 and
A/D_1, which makes a total of sixteen 16-bit A/D data registers (ADDR). A/D conversion
results are stored in A/D data registers (ADDR) that correspond to the input channels.
• Sample-and-hold function
A sample-and-hold circuit is built into the A/D converter of this LSI, simplifying the
configuration of the external analog input circuitry. Multiple channels can be sampled
simultaneously because sample-and-hold circuits can be dedicated for channels 0 to 2 and 8 to
10.
 Group A (GrA): Analog input pins selected from channels 0, 1, and 2 can be
simultaneously sampled.
 Group B (GrB): Analog input pins selected from channels 8, 9, and 10 can be
simultaneously sampled.
• Three methods for starting conversion
Software: Setting of the ADST bit in ADCR
Timer: TRGAN, TRG0N, TRG4AN, and TRG4BN from the MTU2
TRGAN, TRG4AN, and TRG4BN from the MTU2S
External trigger: ADTRG (LSI pin)
Rev. 2.00 Sep. 10, 2008 Page 685 of 1130
REJ09B0402-0200