SH7137 Datasheet, PDF (229/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. BSC functions enable this LSI to
connect directly with SRAM and other memory storage devices and external devices.
9.1 Features
1. External address space
• A maximum 1 Mbyte for each of two areas, CS0 and CS1
• The data bus width is fixed to 8 bits for each address space
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), the first cycle is a write
access.
2. Normal space interface
• Supports the interface that can directly connect to the SRAM
Rev. 2.00 Sep. 10, 2008 Page 203 of 1130
REJ09B0402-0200