SH7137 Datasheet, PDF (709/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 I²C Bus Interface 2 (I²C2)
16.8 Usage Note
16.8.1 Module Standby Mode Setting
The I²C2 operation can be disabled or enabled using the standby control register. The initial setting
is for I²C2 operation to be halted. Access to registers is enabled by clearing module standby mode.
For details, refer to section 24, Power-Down Modes.
16.8.2 Issuance of Stop Condition and Repeated Start Condition
A stop condition or repeated start condition should be issued after the fall of the ninth clock pulse
is recognized. The fall of the ninth clock pulse can be recognized by checking the SCLO bit in the
I²C bus control register 2 (ICCR2). When a stop condition or repeated start condition is issued at a
specific timing under the conditions 1 or 2 shown below, the condition may not be output
successfully. Issuance under other than these conditions will succeed with no problem.
1. When the SCL signal did not rise within the time specified in section 16.7, Bit Synchronous
Circuit, due to the load of the SCL bus (load capacitance or pull-up resistor).
2. When the bit synchronous circuit is activated because the low-level periods of the eighth and
ninth clock pulses are extended by the slave device.
16.8.3 Issuance of a Start Condition and Stop Condition in Sequence
Do not issue a start condition and stop condition in sequence. If a start condition and stop
condition are to be issued in sequence, be sure to transmit a slave address before issuing the stop
condition.
Rev. 2.00 Sep. 10, 2008 Page 683 of 1130
REJ09B0402-0200