SH7137 Datasheet, PDF (463/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channels 0 to 4
MPφ
f=
(N + 1)
• Channel 5
f = ^MPφ
N
Where
f:
Counter frequency
MPφ: MTU2 peripheral clock operating frequency
N: TGR set value
10.7.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.120 shows the timing in this case.
MPφ
TCNT write cycle
T1 T2
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.120 Contention between TCNT Write and Clear Operations
Rev. 2.00 Sep. 10, 2008 Page 437 of 1130
REJ09B0402-0200