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SH7137 Datasheet, PDF (29/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 1 Overview
Items
On-chip ROM
On-chip RAM
Bus state controller
(BSC)
Data transfer
controller (DTC)
Interrupt controller
(INTC)
Specification
⢠256 Kbytes
⢠16 Kbytes
⢠Address space: A maximum 1 Mbyte for each of two areas (CS0 and
CS1) (SH7137 only)
⢠8-bit external bus (SH7137 only)
⢠The following features settable for each area independently
 Number of access wait cycles
 Idle wait cycle insertion
 Supports SRAM
⢠Outputs a chip select signal according to the target area
⢠Data transfer activated by an on-chip peripheral module interrupt can
be done independently of the CPU transfer.
⢠Transfer mode selectable for each interrupt source (transfer mode is
specified in memory)
⢠Multiple data transfer enabled for one activation source
⢠Various transfer modes
Normal mode, repeat mode, or block transfer mode can be selected.
⢠Data transfer size can be specified as byte, word, or longword
⢠The interrupt that activated the DTC can be issued to the CPU.
 A CPU interrupt can be requested after one data transfer
completion.
 A CPU interrupt can be requested after all specified data transfer
completion.
⢠Five external interrupt pins (NMI and IRQ3 to IRQ0)
⢠On-chip peripheral interrupts: Priority level set for each module
⢠Vector addresses: A vector address for each interrupt source
Rev. 2.00 Sep. 10, 2008 Page 3 of 1130
REJ09B0402-0200
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