SH7137 Datasheet, PDF (539/1160 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
12.3.8 Port Output Enable Control Register 2 (POECR2)
POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
MTU2 MTU2 MTU2
P1CZE P2CZE P3CZE
-
MTU2S MTU2S MTU2S
P1CZE P2CZE P3CZE
-
-
-
-
-
-
-
-
Initial value: 0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
R/W: R R/W* R/W* R/W* R R/W* R/W* R/W* R
R
R
R
R
R
R
R
Note: * Can be modified only once after a power-on reset.
Initial
Bit
Bit Name
value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
MTU2P1CZE 1
R/W* MTU2 Port 1 Output Comparison/High-Impedance
Enable
This bit specifies whether to compare output levels on
the large current pins for the MTU2, PE9/TIOC3B and
PE11/TIOC3D, and to place them in the high-
impedance state when the OSF1 bit is set to 1 while
the OCE1 bit is 1 or when any one of the POE0F,
POE1F, POE2F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
the high-impedance state
1: Compares output levels and places the pins in the
high-impedance state
13
MTU2P2CZE 1
R/W* MTU2 Port 2 Output Comparison/High-Impedance
Enable
This bit specifies whether to compare output levels on
the large current pins for the MTU2, PE12/TIOC4A
and PE14/TIOC4C, and to place them in the high-
impedance state when the OSF1 bit is set to 1 while
the OCE1 bit is 1 or when any one of the POE0F,
POE1F, POE2F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
the high-impedance state
1: Compares output levels and places the pins in the
high-impedance state
Rev. 2.00 Sep. 10, 2008 Page 513 of 1130
REJ09B0402-0200